1. Field of the Invention
The present invention relates to a counter for counting a predetermined number of clocks, and, more particularly, to a counter suitable for being incorporated in an integrated circuit using a high speed clock.
2. Description of the Related Art
There is a counter which outputs a pulse when a predetermined number of clocks is input by using a synchronized counter circuit synchronizing clocks. Such counter is widely used, for example, for generating a horizontal synchronizing signal for a display device.
FIG. 6 is a block diagram of a conventional counter counting a predetermined number of clocks. A counter 60 counts the number of clocks CLK with a counter circuit 61, and a comparator 62 compares count values (Q0-Qn) from the counter circuit 61 with externally set values HDB (HDB0-HDBn) indicative of a predetermined number, and outputs a count complete signal OUT when both value match each other. The counter circuit 61 is initialized with a reset signal RST. In addition, the comparator 62 consists of, for example, an EX-NOR circuit, and the count value (Q0-Qn) being input and the externally set value HDB (HDB0-HDBn) have the same number of bits.
Typically, a circuit shown in FIG. 7 is used for the counter circuit 61. A counter circuit 70 consists of D-type flip-flops 700-70n which are output circuits to which a clock signal CLK is commonly input, and a feedback section 71 for carrying the count value. The count value is represented by a BCD code, where Q0 is LSB, and Qn is MSB. Here, the operating frequency of this circuit mainly depends on the working speed of the feedback section 71. That is, since the feedback section 71 consists of an inverter 710, and gate circuits such as EX-OR circuits 720-72n and AND circuits 730-73n, the maximum possible operating frequency of the counter circuit 70 depends on gate delay of the gate circuits constituting the feedback section 71.
Recently, the integrate circuit is demanded for high speed operation, and the frequency becomes higher accordingly for the clock signal used in the integrated circuit. However, in the counter circuit 70, when the frequency of clock signal CLK becomes higher, carrying of the count value may late for input of the clock signal CLK due to gate delay in a feedback section 71, leading to malfunction. Therefore, recently, without using the counter circuit as in FIG. 7, it is contemplated to increase speed of the counting operation by constructing a counter only with shift registers and flip-flops. However, such counter circuit has a problem in a scale of circuit and power consumption.